Method and apparatus for a deposited fill layer

ABSTRACT

A method of forming a semiconducting wafer is provided that utilizes fewer processing operations, reduces process variation, and lowers cost as well as production time. The method provided further improves via reliability by permitting vias to be formed with consistent aspect ratios. Devices and method are provided that substantially eliminate four way intersections on semiconductor wafers between conducting elements and supplemental elements. The devices and methods provide a more uniform deposition rate of a subsequent dielectric layer. Four way intersections are removed from both conductive element regions as well as supplemental element regions.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation of U.S. application Ser. No.10/745,311, filed Dec. 22, 2003, which is a Divisional of U.S.application Ser. No. 10/230,960, filed Aug. 29, 2002, now U.S. Pat. No.6,667,531, which are both incorporated herein by reference.

This application is related to the following co-pending, commonlyassigned U.S. patent application Ser. No. 10/232,853, filed Aug. 28,2002, now U.S. Pat. No. 6,898,779; of which the disclosure is hereinincorporated by reference in its entirety.

FIELD OF THE INVENTION

The invention relates to semiconductor wafers and semiconductor devicesand their fabrication. Specifically, the invention relates to methods offabricating layers on a semiconductor wafer, and the semiconductordevices that result from the methods.

BACKGROUND OF THE INVENTION

Semiconductor integrated circuits are formed using large numbers ofcomplex processing operations to form several layers of devices andelectrical connections stacked on top of each other. Isolating layers ofdielectric material are needed to electrically isolate semiconductordevices and electrical connecting lines from each other. The dielectricmaterial is typically deposited in lateral spaces between elements suchas semiconductor devices and between electrical connections such astrace lines. The dielectric material is also deposited between multiplelayers of devices or connections to isolate portions of layers from eachother.

FIG. 1 shows an integrated circuit 100, including a semiconductorsubstrate 110. The integrated circuit 100 includes a number ofsemiconductor devices 120 that are formed on, or within the substrate110. Electrical connections such as first electrical connection 130 andsecond electrical connection 132 are included for interconnectingselected semiconductor devices 120.

Current fabrication methods utilize a multiple step process to isolatevarious elements of the integrated circuit 100 as described. A firstdielectric layer 150 is included in the multiple step process. The firstdielectric layer 150 is shown in FIG. 1 located over the electricalconnections 130 and 132. The dielectric layer 150 in commonconfigurations is a conformal layer that contacts both a substrateelevation level area 112 and an element elevation level area 114.

One current technique also utilizes supplemental structures such asstructure 140 to minimize the amount of surface area on the substrate110 that is at the substrate elevation level 112. However, with theconfiguration shown in FIG. 1, there is still a substantial differencein elevation between the substrate elevation level 112 and the elementelevation level 114. The conformal dielectric layer 150 of the currentprocess does not yield a planar outer surface.

It is desirable to form a substantially planar outer surface so thatstacks of layers including subsequent semiconductor devices orelectrical connections can be formed as needed. Using the currentprocess, additional dielectric layers such as second dielectric layer160 are needed to form a substantially planar outer surface 162. Theouter surface 162 is made planar by selecting the second dielectricmaterial and deposition process such that remaining recesses 163 arefilled in.

Currently, no process or product exists that forms the substantiallyplanar outer surface 162 in a single processing operation, with a singlelayer of material. Multiple process operations, while often necessary,are undesirable because of added time and manufacturing cost associatedwith each additional operation.

A via 170 is further shown in FIG. 1, formed through the firstdielectric layer 150 and the second dielectric layer 160. The via 170 isneeded when utilizing subsequent device or electrical connection layers,to form an electrical contact that communicates with, for example, thesecond electrical connection 132 as shown.

The via 170 includes a via width 172. Because the via 170 passes throughboth the first dielectric layer 150 and the second dielectric layer 160in order to reach the second electrical connection 132, the via has aheight that is equal to a thickness 166. The thickness 166 is equal to afirst dielectric layer thickness 152 added to a second dielectric layerthickness 164. The via 170 has an aspect ratio equal to its height overits width 172. Due to thickness variations introduced in each depositionoperation, there is a large variation in aspect ratios of vias formedafter two dielectric depositions. High aspect ratio vias can bedifficult to fill with conductive material in later processingoperations. Aspect ratio variations are thus undesirable because of theresulting low reliability of high aspect ratio vias.

What is needed is a method of processing a semiconductor wafer to form asemiconductor device or integrated circuit that uses fewer processingsteps. What is also needed is a method of processing a semiconductorwafer to form a semiconductor device or integrated circuit that allowsmore controlled variation of via aspect ratios.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an elevational view of an integrated circuit according tothe prior art.

FIG. 2 shows a plan view of an integrated circuit according to the priorart.

FIG. 3A shows a plan view of one embodiment of an integrated circuitaccording to the invention.

FIG. 3B shows a plan view of another embodiment of an integrated circuitaccording to the invention.

FIG. 4A shows an elevational view of a semiconductor wafer duringprocessing according to one embodiment of the invention.

FIG. 4B shows an elevational view of a semiconductor wafer duringprocessing according to one embodiment of the invention.

FIG. 4C shows an elevational view of a semiconductor wafer duringprocessing according to one embodiment of the invention.

FIG. 4D shows an elevational view of a semiconductor wafer according toanother embodiment of the invention.

FIG. 5 shows a perspective view of an information handling deviceaccording to one embodiment of the invention.

FIG. 6 shows a schematic view of a central processing unit according toone embodiment of the invention.

FIG. 7 shows a schematic view of a memory device according to oneembodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the invention, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown, by way of illustration, specific embodiments in which theinvention may be practiced. In the drawings, like numerals describesubstantially similar components throughout the several views. Theseembodiments are described in sufficient detail to enable those skilledin the art to practice the invention. Other embodiments may be utilizedand structural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The terms wafer andsubstrate used in the following description include any structure havingan exposed surface with which to form the integrated circuit (IC)structure of the invention. The term substrate is understood to includesemiconductor wafers. The term substrate is also used to refer tosemiconductor structures during processing, and may include other layersthat have been fabricated thereupon. Both wafer and substrate includedoped and undoped semiconductors, epitaxial semiconductor layerssupported by a base semiconductor or insulator(semiconductor-on-insulator—SOD), as well as other semiconductorstructures well known to one skilled in the art. The term conductor isunderstood to include semiconductors, and the term insulator ordielectric is defined to include any material that is less electricallyconductive than the materials referred to as conductors.

The term “horizontal” or “lateral” as used in this application isdefined as a plane parallel to the conventional plane or surface of awafer or substrate, regardless of the orientation of the wafer orsubstrate. The term “vertical” or “elevational” refers to a directionperpendicular to the horizontal as defined above. Prepositions, such as“on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under”are defined with respect to the conventional plane or surface being onthe top surface of the wafer or substrate, regardless of the orientationof the wafer or substrate.

The term “trench” is used in the present application to refer to a spacebetween elements. One form of a trench is created by building upelements on a surface, thus creating spaces between the elements.Another form of trench is created by removing material from asubstantially continuous layer to create elements. The spaces betweenthe elements of the layer are also defined as trenches.

The following detailed description is, therefore, not to be taken in alimiting sense. The scope of the present invention is defined only bythe appended claims, along with the full scope of equivalents to whichsuch claims are entitled.

FIG. 2 shows a current design of an integrated circuit (IC) 200. The IC200 is formed on a substrate 210, and includes a first region 220containing a number of conductive elements 222. In one embodiment, theconductive elements 222 include metal trace lines as are commonly knownin the art. The IC 200 further includes a second region 230 that doesnot require any conductive elements 222. For a variety of reasons, anumber of second regions 230 that do not require any conductive elements222 may be included across a surface of a semiconductor wafer or an IC.

The conductive elements 222 shown in FIG. 2 extent outward from thesubstrate 210 to an elevation. The conductive elements 222 thereforedefine a number of trenches between individual conductive elements. Agenerally linear first trench 224 is shown with a first trench axis 225.A generally linear second trench 226 is also shown with a second trenchaxis 227. In the current embodiment of FIG. 2, an intersection 228 isshown where the first trench axis 225 crosses over the second trenchaxis 227. The intersection forms a “four way intersection” which isdistinguishable from a “three way intersection” such as secondintersection 229. In a three way intersection, the trench axes meet, butthey do not cross one another.

It has recently been noted that during a dielectric layer depositionbetween elements on a substrate such as conductive elements 222, thatfour way intersections fill more slowly than other trench topography.Deposition over elements that include four way intersections isdifficult due to the differences in fill rate. A single layer depositionis impractical because the four way intersections do not fill in aplanar manner. When a second layer is used to planarize a surface overfour way intersections, additional variations in thickness result thatmust be tunneled through if a via is to be connected to a conductiveelement below.

FIG. 3A shows an IC 300 that does not contain any four wayintersections. The IC 300 is formed on a substrate 310, and includes afirst region 320 containing a number of conductive elements 322. In oneembodiment, the conductive elements 322 include metal trace lines as arecommonly known in the art. In one embodiment, the conductive elements322 are formed from a metal. Possible metals include, but are notlimited to, tungsten, titanium, other refractory metals, or aluminum.Any number of possible shapes of conductive elements are possible. Tracelines, for instance, include straight lines, 90 degree turns, and othercomplex geometry. Functionally, the conductive elements must merelyinterconnect two or more semiconductor devices, such as transistors, toeach other.

The IC 300 further includes a second region 330 that does not requireany conductive elements 322. Any number of such regions 330 that do notrequire any conductive elements may be spread across the surface of thesemiconductor substrate 310 in the IC 300. FIG. 3A shows a substantiallysquare second region 330, however, other shapes including multiple sidedcomplex shapes are also included in alternate embodiments. The exactshape of any of a number of second regions 330 is determined bylocations of semiconductor devices, such as transistors, that requireinterconnection through conductive elements such as 322.

The conductive elements 322 shown in FIG. 3A extent outward from thesubstrate 310 to an elevation. The conductive elements 322 thereforedefine a number of trenches between individual conductive elements. Agenerally linear first trench 324 is shown with a first trench axis 325.A generally linear second trench 326 is also shown with a second trenchaxis 327. An intersection 328 is shown where the first trench axis 325meets the second trench axis 327. The intersection forms a three wayintersection as described above. The first trench axis 325 meets, butdoes not cross, the second trench axis 327.

FIG. 3B shows the IC 300 with a further addition of a number ofsupplemental elements 350. The supplemental elements 350 are locatedwithin the second region 330. The supplemental elements 350 include avariety of possible shapes. Example shapes from one embodiment are shownin FIG. 3B as squares, “cross” shapes, and partial “cross” shapes. Inone embodiment, the supplemental elements 350 are formed from a metal.The supplemental elements are not required to conduct electricalsignals, therefore they need not be conductive. In one embodiment, thesupplemental elements 350 are formed from the same material as theconductive elements 322. In one embodiment, the supplemental elementsare formed in a single process operation along with the conductiveelements.

The use of supplemental elements aids in the subsequent step ofisolation using a dielectric layer as described above. If the secondregion 330 is left open the deposition process kinetics lead to adepression in the second region while the dielectric material layerdeposits more fully in “trenched” areas such as 320. A more uniformdeposition process is achieved when spaces between all elements aresubstantially the same. In the embodiments shown in FIGS. 3A and 3B, thetrenches shown are all substantially the same width as measuredperpendicular to the trench axes, thus in the embodiments shown in FIGS.3A and 3B, spaces between all elements are substantially the same.

The supplemental elements 350 shown in FIG. 3B extent outward from thesubstrate 310 to an elevation. In one embodiment, the elevation of thesupplemental elements 350 is substantially the same as the elevation ofthe conductive elements 322. The supplemental elements 350 thereforedefine a number of trenches between individual supplemental elements. Agenerally linear third trench 332 is shown with a third trench axis 333.A generally linear fourth trench 334 is also shown with a fourth trenchaxis 335. An intersection 336 is shown where the third trench axis 333meets the fourth trench axis 335. The intersection forms a three wayintersection as described above. The third trench axis 333 meets, butdoes not cross, the fourth trench axis 335.

The IC 300 does not include any four way intersections in either thefirst region 320 or the second region 330. This design has a number ofadvantages. First, filling in regions such as 330 and making spaces allsubstantially equal in regions such as 320 and 330 makes the photopatterning more robust, and the dry etch patterning more uniform. Then,by eliminating four way intersections, the subsequent dielectricdeposition process kinetics are further improved beyond the kineticsachieved with the substantially equal spaces. By eliminating four wayintersections, all regions tend to fill more uniformly, which allows athinner dielectric layer deposition that fills all holes. Additionally,the even fill rate of this novel design allows the isolation layer to beformed in a single process operation. The single layer deposition with auniform fill rate does not leave pits or deep depressed regions thatneed to be filled by a subsequent material and deposition operation. Theresulting dielectric layer possesses a substantially planar top surface,(max.−min. topographic feature height differences of approximately200-500 Å and only introduces thickness variations from a single processstep in contrast to a two layer deposition. In one embodiment, asubsequent buffing operation further removes the 200-500 Å surfaceroughness variation in preparation for subsequent semiconductor devicelayers. A dielectric layer with less localized thickness variation, aswell as less global thickness variation, is thus produced using thenovel design methods as described above.

FIG. 4A shows a semiconductor wafer that includes a substrate 410 and anumber of semiconductor devices 420 formed within the substrate 410. Oneskilled in the art will recognize that semiconductor devices 420 mayalso be formed partially within the substrate 410, or merely attached toa surface of the substrate 410. Semiconductor devices 420 include, butare not limited to transistors, storage capacitors, diodes, etc.

FIG. 4B shows the addition of a first conducting element 430 and asecond conducting element 432. Selected semiconductor devices 420 areinterconnected by the first conducting element 430. Also shown is asupplemental element 440.

FIG. 4C shows a dielectric layer 450 that is deposited over theconducting elements 430, 432 and the supplemental element 440. Thedielectric layer is deposited to a thickness 452. As described above,the thickness 452 is more reproducible, locally across the wafer, aswell as from wafer to wafer within a production fabrication. At the sametime, a dielectric surface 454 is substantially planar to allowsubsequent layers of semiconductor devices or additional conductingelement layers to be applied without additional surface preparation.

FIG. 4D shows a via 460 that has been created within the dielectriclayer 450. The via 460 has a height 462 and a width 464 that define anaspect ratio of the via 460. The via 460 can be formed in the singledeposition dielectric layer 450 with a much more consistent aspect ratiodue to the more consistent thickness 452 of the dielectric layer 450.This yields a more reliable IC because the vias 460 are consistentlyeasy to fill with conductive material in contrast to IC's that havevariations in thickness and include higher aspect ratio vias.

Semiconducting wafers and IC's created by the methods described abovemay be implemented into memory devices and information handling devicesas shown in FIG. 5, FIG. 6, and FIG. 7 and as described below. Whilespecific types of memory devices and computing devices are shown below,it will be recognized by one skilled in the art that several types ofmemory devices and information handling devices could utilize theinvention.

A personal computer, as shown in FIGS. 5 and 6, includes a monitor 500,keyboard input 502 and a central processing unit 504. The processor unittypically includes microprocessor 606, memory bus circuit 608 having aplurality of memory slots 612(a-n), and other peripheral circuitry 610.Peripheral circuitry 610 permits various peripheral devices 624 tointerface processor-memory bus 620 over input/output (I/O) bus 622. Thepersonal computer shown in FIGS. 5 and 6 also includes at least onetransistor having a gate oxide according to the teachings of the presentinvention.

Microprocessor 606 produces control and address signals to control theexchange of data between memory bus circuit 608 and microprocessor 606and between memory bus circuit 608 and peripheral circuitry 610. Thisexchange of data is accomplished over high speed memory bus 620 and overhigh speed I/O bus 622.

Coupled to memory bus 620 are a plurality of memory slots 612(a-n) whichreceive memory devices well known to those skilled in the art. Forexample, single in-line memory modules (SIMMs) and dual in-line memorymodules (DIMMs) may be used in the implementation of the presentinvention.

These memory devices can be produced in a variety of designs whichprovide different methods of reading from and writing to the dynamicmemory cells of memory slots 612. One such method is the page modeoperation. Page mode operations in a DRAM are defined by the method ofaccessing a row of a memory cell arrays and randomly accessing differentcolumns of the array. Data stored at the row and column intersection canbe read and output while that column is accessed. Page mode DRAMsrequire access steps which limit the communication speed of memorycircuit 608. A typical communication speed for a DRAM device using pagemode is approximately 33 MHZ.

An alternate type of device is the extended data output (EDO) memorywhich allows data stored at a memory array address to be available asoutput after the addressed column has been closed. This memory canincrease some communication speeds by allowing shorter access signalswithout reducing the time in which memory output data is available onmemory bus 620. Other alternative types of devices include SDRAM, DDRSDRAM, SLDRAM and Direct RDRAM as well as others such as SRAM or Flashmemories.

FIG. 7 is a block diagram of an illustrative DRAM device 700 compatiblewith memory slots 612(a-n). The description of DRAM 700 has beensimplified for purposes of illustrating a DRAM memory device and is notintended to be a complete description of all the features of a DRAM.Those skilled in the art will recognize that a wide variety of memorydevices may be used in the implementation of the present invention. Theexample of a DRAM memory device shown in FIG. 7 includes at least onetransistor having a gate oxide according to the teachings of the presentinvention.

Control, address and data information provided over memory bus 620 isfurther represented by individual inputs to DRAM 700, as shown in FIG.7. These individual representations are illustrated by data lines 702,address lines 704 and various discrete lines directed to control logic706.

As is well known in the art, DRAM 700 includes memory array 710 which inturn comprises rows and columns of addressable memory cells. Each memorycell in a row is coupled to a common wordline. Additionally, each memorycell in a column is coupled to a common bitline. Each cell in memoryarray 710 includes a storage capacitor and an access transistor as isconventional in the art.

DRAM 700 interfaces with, for example, microprocessor 606 throughaddress lines 704 and data lines 702. Alternatively, DRAM 700 mayinterface with a DRAM controller, a micro-controller, a chip set orother electronic system. Microprocessor 606 also provides a number ofcontrol signals to DRAM 700, including but not limited to, row andcolumn address strobe signals RAS and CAS, write enable signal WE, anoutput enable signal OE and other conventional control signals.

Row address buffer 712 and row decoder 714 receive and decode rowaddresses from row address signals provided on address lines 704 bymicroprocessor 606. Each unique row address corresponds to a row ofcells in memory array 710. Row decoder 714 includes a wordline driver,an address decoder tree, and circuitry which translates a given rowaddress received from row address buffers 712 and selectively activatesthe appropriate wordline of memory array 710 via the wordline drivers.

Column address buffer 716 and column decoder 718 receive and decodecolumn address signals provided on address lines 704. Column decoder 718also determines when a column is defective and the address of areplacement column. Column decoder 718 is coupled to sense amplifiers720. Sense amplifiers 720 are coupled to complementary pairs of bitlinesof memory array 710.

Sense amplifiers 720 are coupled to data-in buffer 722 and data-outbuffer 724. Data-in buffers 722 and data-out buffers 724 are coupled todata lines 702. During a write operation, data lines 702 provide data todata-in buffer 722. Sense amplifier 720 receives data from data-inbuffer 722 and stores the data in memory array 710 as a charge on acapacitor of a cell at an address specified on address lines 704.

During a read operation, DRAM 700 transfers data to microprocessor 606from memory array 710. Complementary bitlines for the accessed cell areequilibrated during a precharge operation to a reference voltageprovided by an equilibration circuit and a reference voltage supply. Thecharge stored in the accessed cell is then shared with the associatedbitlines. A sense amplifier of sense amplifiers 720 detects andamplifies a difference in voltage between the complementary bitlines.The sense amplifier passes the amplified voltage to data-out buffer 724.

Control logic 706 is used to control the many available functions ofDRAM 700. In addition, various control circuits and signals not detailedherein initiate and synchronize DRAM 700 operation as known to thoseskilled in the art. As stated above, the description of DRAM 700 hasbeen simplified for purposes of illustrating the present invention andis not intended to be a complete description of all the features of aDRAM.

Those skilled in the art will recognize that a wide variety of memorydevices, including but not limited to, SDRAMs, SLDRAMs, RDRAMs and otherDRAMs and SRAMs, VRAMs and EEPROMs, may be used in the implementation ofthe present invention. The DRAM implementation described herein isillustrative only and not intended to be exclusive or limiting.

CONCLUSION

Thus has been shown a method of forming a semiconducting wafer thatutilizes fewer processing operations than prior methods. The methodshown further improves reliability of the devices formed by permittingvias to be formed with more consistent aspect ratios.

The present teachings recognize, among other novel aspects, that arelation of a fundamental wafer design that affects properties such asdeposition kinetics. One specific teaching recognizes that eliminationof four way intersections on semiconductor wafers between conductingelements and supplemental elements yields a more uniform deposition rateof a subsequent dielectric layer. In embodiments described above, fourway intersections are removed from both conductive element regions aswell as supplemental element regions.

The more uniform deposition rate allows use of a single processoperation to deposit a thin, consistent dielectric layer that includes asubstantially planar surface. The thinner dielectric layer allows a moreconsistent aspect ratio via to interconnect subsequent layers ofsemiconductor devices or conductive elements.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiment shown. This application isintended to cover any adaptations or variations of the presentinvention. It is to be understood that the above description is intendedto be illustrative, and not restrictive. Combinations of the aboveembodiments, and other embodiments will be apparent to those of skill inthe art upon reviewing the above description. The scope of the inventionincludes any other applications in which the above structures andfabrication methods are used. The scope of the invention should bedetermined with reference to the appended claims, along with the fullscope of equivalents to which such claims are entitled.

1. A method of fabricating a semiconductor wafer, comprising: forming apattern of elements on a semiconductor surface, including: forming anumber of conductive elements on the semiconductor surface, theconductive elements being spaced apart from each other; wherein spacesbetween elements of the pattern define a number of trenches with trenchaxes that are substantially parallel to sides of adjacent elements ofthe pattern; designing the pattern to substantially eliminate portionsof the pattern where trench axes cross one another; and filling thenumber of trenches using a single filling operation with a dielectricmaterial to form a substantially planar surface.
 2. The method of claim1, wherein designing the pattern includes designing a pattern to onlyinclude three way trench axes intersections where trenches meet at aright angle.
 3. The method of claim 1, wherein forming a pattern ofelements further includes forming a number of supplemental elements inselected regions on the semiconductor surface adjacent to the number ofconductive elements, the supplemental elements being spaced apart fromeach other and the number of conductive elements.
 4. The method of claim1, wherein forming the number of supplemental elements includes forminga number of supplemental elements from metal.
 5. The method of claim 1,wherein forming a pattern of elements includes forming a spacing betweenelements in the pattern that are substantially the same between allelements.
 6. The method of claim 1, wherein filling the number oftrenches using a single filling operation with a dielectric materialincludes a single filling operation with tetraethylorthosilicate (TEOS).7. The method of claim 1, wherein filling the number of trenches using asingle filling operation with a dielectric material includes a singlefilling operation with silicon dioxide (SiO2).
 8. A method offabricating a semiconductor wafer, comprising: forming a pattern ofelements on a semiconductor surface, including: forming a number ofconductive elements on the semiconductor surface, the conductiveelements being spaced apart from each other; wherein spaces betweenelements of the pattern define a number of trenches with trench axesthat are substantially parallel to sides of adjacent elements of thepattern; and designing the pattern to only include three way trench axesintersections where trenches meet at a right angle.
 9. The method ofclaim 8, wherein forming a pattern of elements further includes forminga number of non-conducting supplemental elements in selected regions onthe semiconductor surface adjacent to the number of conductive elements,the supplemental elements being spaced apart from each other and thenumber of conductive elements.
 10. The method of claim 9, whereinforming a pattern of elements includes forming a spacing betweenelements in the pattern that are substantially the same between allelements.
 11. The method of claim 10, wherein filling the number oftrenches using a single filling operation with a dielectric materialincludes a single filling operation with tetraethylorthosilicate (TEOS).12. The method of claim 10, wherein filling the number of trenches usinga single filling operation with a dielectric material includes a singlefilling operation with silicon dioxide (SiO2).
 13. A method offabricating a semiconductor wafer, comprising: forming a pattern ofelements on a semiconductor surface, including: forming a number ofconductive elements on the semiconductor surface, the conductiveelements being spaced apart from each other; forming a number ofsupplemental elements in selected regions on the semiconductor surfaceadjacent to the number of conductive elements, the supplemental elementsbeing spaced apart from each other and the number of conductiveelements; wherein spaces between elements of the pattern define a numberof trenches with trench axes that are substantially parallel to sides ofadjacent elements of the pattern; and filling the number of trenchesusing a single filling operation with a dielectric material to form asubstantially planar surface.
 14. The method of claim 13, whereinforming a pattern of elements includes forming a spacing betweenelements in the pattern that are substantially the same between allelements.
 15. The method of claim 13, wherein designing the patternincludes designing a pattern to only include three way trench axesintersections where trenches meet at a right angle.
 16. The method ofclaim 13, wherein filling the number of trenches using a single fillingoperation with a dielectric material includes a single filling operationwith tetraethylorthosilicate (TEOS).
 17. The method of claim 13, whereinfilling the number of trenches using a single filling operation with adielectric material includes a single filling operation with silicondioxide (SiO2).